Qualcomm Hexagon

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Hexagon
Designer Qualcomm
Bits 32-bit
Introduced 2006 (QDSP6)
Design 4-way multithreaded VLIW
Type Register-Register
Encoding Fixed 4 byte per instruction, up to 4 instructions in VLIW multiinstruction
Open Proprietary
Registers
General purpose 32-bit GPR: 32, can be paired to 64-bit[1]

Hexagon (QDSP6) is the brand for a family of 32-bit multi-threaded microarchitectures implementing the same instruction set for a digital signal processor (DSP) developed by Qualcomm. According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011 year, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSP[2] (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market[3]).

The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, Very Long Instruction Word (VLIW), Single Instruction, Multiple Data (SIMD),[4] and instructions geared toward efficient signal processing. The CPU is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock.[5][6] Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5.[7][8] Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.[8][9]

Software support

Support for the Hexagon DSPs could be similar to "Texas Instruments' hardware", including some RTOS.

Operating systems

The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"[10]) and was merged with the 3.2 release of the kernel.[11][12] The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a Berkeley Software Distribution (BSD)-style license.[13][14]

Compilers

Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum.[15] There is also a non-FSF maintained branch of GCC and binutils.[16]

Adoption of the SIP block

Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006.[17][18] In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.

They are also used in some femtocell processors of Qualcomm, including FSM9832.[19]

Third party integration

In March 2016, it was announced that semiconductor company Conexant's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon.[20]

Versions

There are four versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011); and QDSP6 V5 (2013, in Snapdragon 800[21]).[18] V4 has 20 DMIPS per milliwatt, operating at 500 MHz.[17][18] Clock speed of Hexagon varies in 400–600 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.[22]

Versions of QDSP6 Process node, nm Date[8] Number of simultaneous threads Per-thread clock, MHz Total core clock, MHz
QDSP6 V1 65[8] Oct 2006
QDSP6 V2[23] 65 Dec 2007[8] 6 100 600
QDSP6 V3 (1st gen)[23] 45 2009 6 67 400
QDSP6 V3 (2nd gen)[23] 45 2009 4 100 400
QDSP6 V4[23] (V4M, V4C, V4L[8]) 28 2010–2011 3[9] 167 500
QDSP6 V5[24] (V5A, V5H[8]) 28 2013 3[8] 200 or greater with DMT[9] 600

Availability in Snapdragon products

Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.

QDSP5 usage:

Snapdragon generation Chipset (SoC) ID DSP Generation DSP Frequency, MHz Process node, nm
S1[22] MSM7627, MSM7227, MSM7625, MSM7225 QDSP5 320 65
S1[22] MSM7627A, MSM7227A, MSM7625A, MSM7225A QDSP5 350 45
S2[22] MSM8655, MSM8255, APQ8055, MSM7630, MSM7230 QDSP5 256 45
S4 Play[22] MSM8625, MSM8225 QDSP5 350 45
S200[25] 8110, 8210, 8610, 8112, 8212, 8612, 8225Q, 8625Q QDSP5 384 45 LP

QDSP6 (Hexagon) usage:

Snapdragon generation Chipset (SoC) ID QDSP6 version DSP Frequency, MHz Process node, nm
S1[22] QSD8650, QSD8250 QDSP6 600 65
S3[22] MSM8660, MSM8260, APQ8060 QDSP6 (V3?) 400 45
S4 Prime[22] MPQ8064 QDSP6 (V3?) 500 28
S4 Pro[22] MSM8960 Pro, APQ8064 QDSP6 (V3?) 500 28
S4 Plus[22] MSM8960, MSM8660A, MSM8260A, APQ8060A, MSM8930,
MSM8630, MSM8230, APQ8030, MSM8627, MSM8227		 QDSP6 (V3?) 500 28
S400[25] 8926, 8930, 8230, 8630, 8930AB, 8230AB, 8630AB, 8030AB, 8226, 8626 QDSP6V4 500 28 LP
S600[25] 8064T, 8064M QDSP6V4 500 28 LP
S800[25] 8974, 8274, 8674, 8074 QDSP6V5A 600 28 HPm

Code sample

This is a single instruction packet from the inner loop of a FFT:[6][9]

{ R17:16 = MEMD(R0++M1)
  MEMD(R6++M1) = R25:24
  R20 = CMPY(R20, R8):<<1:rnd:sat
  R11:10 = VADDH(R11:10, R13:12)
}:endloop0

This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.

See also

References

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External links

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