ARM Cortex-A76

The ARM Cortex-A76 is a microarchitecture implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. The Cortex-A76 frontend is a 4-wide decode out-of-order superscalar design. The backend is 8 execution ports with a pipeline depth of 13 stages and the execution latencies of 11 stages.

Design

The Cortex-A76 serves as the successor of the Cortex-A73 and Cortex-A75, though based on a clean sheet design. The core supports unprivileged 32-bit applications, but privileged applications must utilize the 64-bit ARMv8-A ISA. It also supports Load acquire (LDAPR) instructions (ARMv8.3-A), Dot Product instructions (ARMv8.4-A), PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB, PSSBB) instructions (ARMv8.5-A).

ARM announced 25% and 35% increases in integer and floating point performance, respectively. Memory bandwidth increased 90% relative to the A75. According to ARM, the A76 is expected to offer twice the performance of an A73 and is targeted beyond mobile workloads. The performance is targeted at "laptop class", including Windows 10 devices, competitive with Intel's Kaby Lake.

The Cortex-A76 support ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with Cortex-A55 power-efficient cores.

Licensing

The Cortex-A76 is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A76, used within their high-end Kryo 495 (Snapdragon 8cx)/Kryo 485 (Snapdragon 855) and mid-range Kryo 460 (Snapdragon 675) CPUs. One of the modifications Qualcomm made was increasing reorder buffer to increase the out-of-order window size.