MERSI protocol

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The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4.[1] The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.[2]

For any given pair of caches, the permitted states of a given cache line are as follows:

 M   E   R   S   I 
 M  Red XN Red XN Red XN Red XN Green tickY
 E  Red XN Red XN Red XN Red XN Green tickY
 R  Red XN Red XN Red XN Red XN Green tickY
 S  Red XN Red XN Red XN Green tickY Green tickY
 I  Green tickY Green tickY Green tickY Green tickY Green tickY

References

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  1. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  2. ↑ US Patent 6857051, http://www.google.com/patents/about?id=ZtsVAAAAEBAJ&dq=6857051
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