NAND logic

This article is about NAND Logic in the sense of building other logic gates using just NAND gates. For NAND Gates, see NAND gate. For NAND in the purely logical sense, see Logical NAND. For logic gates generally, see Logic gate.

Because the NAND function has functional completeness all logic systems can be converted into NAND gates. This is also true of NOR gates. In principle, any combinatorial logic function can be realized with enough NAND gates.

NAND

A NAND gate is an inverted AND gate. It has the following truth table:

Q = NOT( A AND B ) Truth Table Input A Input B Output Q 0 0 1 0 1 1 1 0 1 1 1 0

NOT

A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.

Desired NOT Gate	NAND Construction
File:NOT ANSI Labelled.svg	File:NOT from NAND.svg
Q = NOT( A )	= NOT( A AND A )
Truth Table Input A Output Q 0 1 1 0

AND

An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND.

Desired AND Gate	NAND Construction
Q = A AND B	= NOT[ NOT( A AND B ) AND NOT( A AND B ) ]
Truth Table Input A Input B Output Q 0 0 0 0 1 0 1 0 0 1 1 1

OR

If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

Desired OR Gate	NAND Construction
File:OR ANSI Labelled.svg	File:OR from NAND.svg
Q = A OR B	= NOT[ NOT( A AND A ) AND NOT( B AND B )]
Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 1

NOR

A NOR gate is simply an inverted OR gate. Output is high when neither input A nor input B is high:

Desired NOR Gate	NAND Construction
Q = NOT( A OR B )	= NOT{ NOT[ NOT( A AND A ) AND NOT( B AND B )] AND NOT[ NOT( A AND A ) AND NOT( B AND B )] }
Truth Table Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 0

XOR

An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if both inputs are high, the inputs to the final NAND gate will also be high, and the output will be low.

Desired XOR Gate	NAND Construction
File:XOR ANSI Labelled.svg	File:XOR from NAND.svg
Q = A XOR B	= NOT{ NOT[ A AND NOT( A AND B ) ] AND NOT[ B AND NOT( A AND B ) ] }
Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 0

If you create 3 random or any chosen bit vectors or single bits, and xor each pair on a side, then those new 3 values, each 2 of them xored together cancel the value which is part of both, leaving the other 2 values which, any direction around the 3, 2 of them xor to the other. This is similarly extended to n bits/vectors xored and combining them to remove those shared. This is set theory, such as other basic gates can describe the union, intersection, or one side asymmetricly since xor can create any of those parts.

Xor is not entirely balanced between 1 and 0, so just because a few can't form the same logic as other basic gates does not mean that all possible ways to use them are so limited. Clique Cover is easier than Minimum Clique Cover, while both look the same in most observations, until you may search a nearly powerset of possible cliques a little bigger. The output of x vars xored can often be the same as y vars xored, but not all such vars are connected to symmetric other xor logic. An individual XOR is equally often 0 or 1 on either side, and if one is random the pattern in the other will be undetectable by those 2 bit variables alone. But in larger groups of the same ratio of 1s to 0s (half of each), we may count the bit variables instead of counting the gates which are between pairs. There are more pairs in all xors on 4 bits than the ratio of 1s to 0s since each xor has all the opposite bit value to pair with, but 1 less of its own bit value since it doesnt pair with itself. It does, by the same logic, have its own bit value since that only takes 1 var. Or if it does pair with itself, it has done it 2 times.

XNOR

An XNOR gate is simply an XOR gate with an inverted output:

Desired XNOR Gate	NAND Construction
File:XNOR ANSI Labelled.svg	File:XNOR from NAND.svg
Q = NOT( A XOR B)	= NOT( NOT{ NOT[ A AND NOT( A AND B ) ] AND NOT[ B AND NOT( A AND B ) ] } AND NOT{ NOT[ A AND NOT( A AND B ) ] AND NOT[ B AND NOT( A AND B ) ] } )

Truth Table

Input A	Input B		Output Q
0	0		1
0	1		0
1	0		0
1	1		1

See also

• NOR logic. Like NAND gates, NOR gates are also universal gates.
• Functional Completeness

External links

• TTL NAND and AND gates - All About Circuits
• Steps to Derive XOR from NAND gate.
• NAND Gate, Demonstrate an interactive simulation of the NAND Gate circuit created with Teahlab's simulator.