Silicon on sapphire
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Silicon on sapphire (SOS) is a hetero-epitaxial process for integrated circuit manufacturing that consists of a thin layer (typically thinner than 0.6 µm) of silicon grown on a sapphire (Al2O3) wafer. SOS is part of the Silicon on Insulator (SOI) family of CMOS technologies. Typically, high-purity artificially grown sapphire crystals are used. The silicon is usually deposited by the decomposition of silane gas (SiH4) on heated sapphire substrates. The advantage of sapphire is that it is an excellent electrical insulator, preventing stray currents caused by radiation from spreading to nearby circuit elements. SOS faced early challenges in commercial manufacturing because of difficulties in fabricating the very small transistors used in modern high-density applications. This is because the SOS process results in the formation of dislocations, twinning and stacking faults from crystal lattice disparities between the sapphire and silicon. Additionally, there is some aluminum, a p-type dopant, contamination from the substrate in the silicon closest to the interface.
Contents
History
In 1963, Dr. Harold M. Manasevit was the first to document epitaxial growth of silicon on sapphire while working at the North American Aviation Autonetics Division (now Boeing). In 1964, he published his findings with colleague William Simpson in the Journal of Applied Physics. [1]
SOS was first used in aerospace and military applications because of its inherent resistance to radiation. More recently, patented advancements in SOS processing and design have been made by Peregrine Semiconductor, allowing SOS to be commercialized in high-volume for high-performance radio-frequency (RF) applications.
Circuits and Systems
The advantages of the SOS technology allow research groups to fabricate a variety of SOS circuits and systems that benefit from the technology and advance the state-of-the-art in:
- analog-to-digital converters (a nano-Watts prototype was produced by Yale e-Lab)[2]
- monolithic digital isolation buffers[3]
- SOS-CMOS image sensor arrays (one of the first standard CMOS image sensor arrays capable of transducing light simultaneously from both sides of the die was produced by Yale e-Lab)[4]
- patch-clamp amplifiers[5]
- energy harvesting devices[6]
- three-dimensional (3D) integration with no galvanic connections
- charge pumps[7]
- temperature sensors[8]
Additional Reading: "Silicon-on-Sapphire Circuits and Systems, Sensor and Biosensor interfaces" by Eugenio Culurciello published by McGraw Hill in 2009.
Applications
Silicon on sapphire pressure and temperature sensors have been manufactured by Sensotron and Sensonetics utilizing a process by Armen Sahagen.[9] And ESI Technology Ltd in the UK have developed a wide range of pressure transducers and pressure transmitters that benefit from the outstanding features of silicon on sapphire. [10]
San Diego-based Peregrine Semiconductor has used silicon on sapphire (SOS) technology to develop RF integrated circuits (RFICs) including RF switches, digital step attenuators (DSAs), phase locked-loop (PLL) frequency synthesizers, prescalers, mixers/upconverters, and variable-gain amplifiers. These RFICs are designed for commercial RF applications such as mobile handsets and cellular infrastructure, broadband consumer and DTV, test and measurement, and industrial public safety, as well as rad-hard aerospace and defense markets.
Hewlett Packard originally used silicon on sapphire integrated circuits on their HP Voyager series calculators featuring the proprietary HP Nut processor, that are praised for their long lasting batteries. Later calculator revisions used other processors.
Substrate Analysis - SOS Structure
The application of epitaxial growth of silicon on sapphire substrates for fabricating MOS devices involves a silicon purification process that mitigates crystal defects which result from a mismatch between sapphire and silicon lattices. For example, Peregrine Semiconductor's SP4T switch is formed on an SOS substrate where the final thickness of silicon is approximately 95 nm. Silicon is recessed in regions outside the polysilicon gate stack by poly oxidation and further recessed by the sidewall spacer formation process to a thickness of approximately 78 nm.
See also
References
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- ↑ http://www.eng.yale.edu/elab/publications/ADCTCASII2006.pdf]http://www.eng.yale.edu/elab/publications/2c1cisosadc.pdf
- ↑ http://www.eng.yale.edu/elab/publications/isoAICSP2006.pdf
- ↑ http://www.eng.yale.edu/elab/publications/eletsSOSImgrRev1.pdf
- ↑ http://www.eng.yale.edu/elab/publications/iscas06%20patchi06.pdf
- ↑ http://www.eng.yale.edu/elab/publications/pubs/harvestEL2006.pdf
- ↑ http://www.eng.yale.edu/elab/publications/el2005_isolationcp.pdf
- ↑ http://www.eng.yale.edu/elab/publications/EL2006harvest.pdf
- ↑ http://www.sensonetics.com/series420.pdf
- ↑ http://www.esi-tec.com
